Conventional technology for transmitting a clock signal in a semiconductor integrated circuit has imparted the clock signal with a full amplitude on the level of a power-source voltage corresponding to the difference between the power-source voltage and the ground voltage, since static operation is required of a receiving circuit for receiving the clock signal so that the output from the receiving circuit is varied based on the potential change of the clock signal.
With a large-scale chip, the following measures have been taken to minimize a clock skew resulting from a wiring delay (RC delay) so that the clock signal as a synchronization signal changes with the same timing at any portion on an entire chip:
(1) The width of a signal line is increased to reduce the influence of wiring resistance on the clock signal. PA1 (2) Large-size drivers are distributed over the chip.
However, since the amplitude voltage of the clock signal conventionally used in the semiconductor integrated circuit has had the full amplitude on the level of the power-source voltage, power consumption for driving the clock signal is increased disadvantageously.
In the case of increasing the width of the signal line as mentioned in the foregoing measure (1), the wiring resistance may be reduced but the large-size drivers become necessary because of increased wiring capacitance. Therefore, each of the foregoing measures (1) and (2) has the drawback of increased power consumption for driving the clock signal, since the power for driving the drivers is increased.